ADI公司的ADRF6650是高度集成的下變換器,集成了兩個混合器,兩個數字開關衰減器,兩個數字可變增益放大器,一個鎖相環(PLL)和壓控振蕩器(VCO).此外還集成了兩個RF平衡轉換器(Balun),串行增益控制(SGC),用于時分復用(TDD)工作的快速使能輸入.片上的RF平衡轉換器使ADRF6650支持50 Ω終端RF輸入.集成的無源混合器提供高度線性下變換器,用于200MHz滑動中頻(IF)窗口.ADRF6650采用寬帶方波限幅振蕩器(LO)放大器,以達到450 MHz 到 2700 MHz的RF帶寬.和通常的窄帶正弦波LO放大器解決方案不同,該放大器允許LO可在極寬帶寬上應用在高于或低下RF輸入頻率.集成的PLL/VCD使得連續LO 的頻率范圍從450 MHz 到 2900 MHz. PLL基準輸入支持寬頻率范圍和包括集成相頻檢測器(PFD)前的基準分頻器.ADRF6650采用先進的硅鍺(SiGe)雙極互補金屬氧化物半導體(BiCMOS)工藝,56引腳RoHS兼容性8 mm × 8 mm LFCSP封裝,工作溫度?40℃ 到 +105℃.主要用在多波段/多標準蜂窩基站分集接收器,寬帶無線連接分集式下變換器,多模式蜂窩擴展器和微微蜂窩基站.本文介紹了ADRF6650主要特性,功能框圖,PLL/VCO框圖,基本連接框圖以及評估板ADRF6650-EVALZ主要特性,測試建立圖,電路圖,材料清單和PCB設計圖.

The ADRF6650 is a highly integrated downconverter that integrates dual mixers, dual digital switched attenuators, dual digital variable gain amplifiers, a phase-locked loop (PLL), and voltage controlled oscillators (VCOs). In addition, the ADRF6650 integrates two radio frequency (RF) baluns, serial gain control (SGC) controls, and fast enable inputs for time division duplex (TDD) operation.

The on-chip RF baluns enable the ADRF6650 to support 50 Ω terminated RF inputs. The integrated passive mixer provides a highly linear downconversion for a 200 MHz, sliding, intermediate frequency (IF) window. The ADRF6650 uses broadband square wave limiting local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional narrow-band sine wave LO amplifier solutions, this amplifier permits the LO to be applied either above or below the RF input over an extremely wide bandwidth. 

The ADRF6650 offers two alternatives for generating the differ-ential LO input signal: internally via the on-chip fractional-N synthesizer with low phase noise VCOs, or externally via a low phase noise LO signal. The integrated PLL/VCO enables contin-uous LO coverage from 450 MHz to 2900 MHz. The PLL reference input supports a wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD). 

The ADRF6650 is fabricated using an advanced silicon-germa-nium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) process. It is available in a 56-lead, RoHS-compliant, 8 mm × 8 mm, lead frame chip scale package (LFCSP) package with an exposed pad. Performance is specified over the ?40℃to +105℃ maximum paddle temperature.

ADRF6650主要特性:

Dual down-converter with integrated fractional-N PLL/VCO 
RF: 450 MHz to 2700 MHz continuous 
LO frequency: 450 MHz to 2900 MHz, high-side or low-side injection 
43 dB gain control range 
Gain control with up/down and SPI 
Integrated RF balun for single-ended 50 Ω inputs 
Power supply: 3.3 and 5 V 
8 mm × 8 mm, 56-lead LFCSP package

ADRF6650應用:

Multiband/multistandard cellular base station diversity receivers 
Wideband radio link diversity downconverters 
Multimode cellular extenders and picocells

圖1.ADRF6650功能框圖

圖2.PLL/VCO框圖

圖3.ADRF6650基本連接框圖

評估板ADRF6650-EVALZ
 
Evaluating the ADRF6650 450 MHz to 2700 MHz Dual Downconverter with DVGA and PLL/VCO
 
The ADRF6650-EVALZ is a 4-layer Rogers printed circuit board (PCB) and evaluates the performance of the ADRF6650. A photograph of the evaluation board is shown in Figure 1. The evaluation board contains the ADRF6650, a connector suited for a SDP-S controller board, power supply connectors, regulators, and subminiature Version A (SMA) connectors. The evaluation board requires an SDP-S controller board to allow software programming of the device. 

The ADRF6650 is a high performance, dual downconverter that integrates mixers, digital switched attenuators, digital variable gain amplifiers (DVGAs), a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). The device uses broadband, square wave limiting, local oscillator (LO) amplifiers to achieve an RF bandwidth of 450 MHz to 2700 MHz. Unlike conventional, narrow-band, sine wave LO amplifier solutions, the ADRF6650 allows the application of the LO either above or below the RF input, over a bandwidth of 450 MHz to 2900 MHz.

This user guide describes the ADRF6650-EVALZ evaluation board and software. For full details, see the ADRF6650 data sheet, which must be consulted in conjunction with this user guide when using the evaluation board.

評估板ADRF6650-EVALZ主要特性:

Full featured evaluation board for the ADRF6650 
Single supply: 5.6 V (1 A capability required) 
ACE software for control 
EVALUATION KIT CONTENTS 
ADRF6650-EVALZ evaluation board

圖4.評估板ADRF6650-EVALZ外形圖

圖5.評估板ADRF6650-EVALZ測試建立圖

圖6.評估板ADRF6650-EVALZ電路圖(1)

圖7.PLL濾波器電路圖

圖8. IF輸出電路圖

圖9.LO輸出電路圖

圖10.外部LO輸入電路圖

圖11.ADRF6650 PLL電路圖

圖12.PLL/VCO電源電路

圖13.RF/IF電源電路

圖14.SDP-S連接器電路
評估板ADRF6650-EVALZ材料清單:




圖15.評估板ADRF6650-EVALZ PCB設計圖(1)

圖16.評估板ADRF6650-EVALZ PCB設計圖(2)
詳情請見:
https://www.analog.com/media/en/technical-documentation/data-sheets/ADRF6650.pdf
和https://www.analog.com/media/en/technical-documentation/user-guides/ADRF6650-EVALZ-UG-1026.pdf
ADRF6650.pdf
ADRF6650-EVALZ-UG-1026.pdf